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IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 32 features ? 144 pin jedec standard, 8 byte small outline dual in-line memory module with 8 byte busses ? 2mx64 extended data out so dimm ? performance: ? all inputs and outputs are lvttl (3.3v) compat- ible ? single 3.3v 0.3v power supply ? au contacts ? optimized for byte-write non-parity applications ? system performance bene?ts: - reduced noise (18 v ss /18v cc pins) - byte write, byte read accesses - serial pds ? extended data out (edo) mode, read-modify- write cycles ? refresh modes: ras-only, cbr hidden refresh, and self refresh ? 2048 refresh cycles distributed across 128ms ? 11/10 addressing (row/column) ? card size: 2.66" x 1.0" x 0.149" ? drams in tsop package description IBM11T2645HP is an industry standard 144-pin 8-byte small outline dual in-line memory module (so dimm) which is organized as a 2mx64 high speed memory array designed for use in non-parity applications. the so dimm uses 8 2mx8 edo drams in tsop packages. the use of edo drams allows for a reduction in page mode cycle time from 40ns (fast page) to 25ns for 60ns edo modules. this card uses serial presence detects implemented via a serial eeprom using the two pin i 2 c protocol. this communication protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (ex: the system micropro- cessor) and the slave eeprom device. the device address for the eeprom is set to zero at the card. the first 128 bytes are utilized by the so dimm manufacturer and the second 128 bytes are avail- able to the end user. all ibm 144-pin so dimms provide a high performance, flexible 8-byte interface in a 2.66 long space-saving footprint. related prod- ucts are the 1mx64, 4mx64 and the x72 (ecc) sodimms. -60 -6r -70 t rac ras access time 60ns 60ns 70ns t cac cas access time 15ns 17ns 20ns t aa access time from address 30ns 30ns 35ns t rc cycle time 104ns 104ns 124ns t hpc edo mode cycle time 25ns 25ns 30ns card outline 1 2 59 60 61 62 143 144 (front) (back) IBM11T2645HP 2m x 6411/10, 3.3v, edommdd41dsu-001019432. discontinued (9/98 - last order; 3/99 last ship)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 32 50h7630 sa14-4460-04 revised 4/97 IBM11T2645HP 2m x 64 144 pin so dimm pin description ras0 row address strobe cas0 - cas7 column address strobe we read/write input oe output enable a0 - a10 address inputs dq0 - dq63 data input/output v cc power (3.3v) v ss ground nc no connect scl serial presence detect clock input sda serial presence detect data input pinout pin# front side pin# back side pin# front side pin# back side 1 v ss 2 v ss 73 oe 74 nc 3 dq0 4 dq32 75 v ss 76 v ss 5 dq1 6 dq33 77 nc 78 nc 7 dq2 8 dq34 79 nc 80 nc 9 dq3 10 dq35 81 v cc 82 v cc 11 v cc 12 v cc 83 dq16 84 dq48 13 dq4 14 dq36 85 dq17 86 dq49 15 dq5 16 dq37 87 dq18 88 dq50 17 dq6 18 dq38 89 dq19 90 dq51 19 dq7 20 dq39 91 v ss 92 v ss 21 v ss 22 v ss 93 dq20 94 dq52 23 cas0 24 cas4 95 dq21 96 dq53 25 cas1 26 cas5 97 dq22 98 dq54 27 v cc 28 v cc 99 dq23 100 dq55 29 a0 30 a3 101 v cc 102 v cc 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 a11 35 v ss 36 v ss 107 v ss 108 v ss 37 dq8 38 dq40 109 a9 110 a12 39 dq9 40 dq41 111 a10 112 a13 41 dq10 42 dq42 113 v cc 114 v cc 43 dq11 44 dq43 115 cas2 116 cas6 45 v cc 46 v cc 117 cas3 118 cas7 47 dq12 48 dq44 119 v ss 120 v ss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 v ss 56 v ss 127 dq27 128 dq59 57 nc 58 nc 129 v cc 130 v cc 59 nc 60 nc 131 dq28 132 dq60 voltage key 133 dq29 134 dq61 61 du 62 du 135 dq30 136 dq62 63 v cc 64 v cc 137 dq31 138 dq63 65 du 66 du 139 v ss 140 v ss 67 we 68 nc 141 sda 142 scl 69 ras0 70 nc 143 v cc 144 v cc 71 nc 72 nc note: all pin assignments are consistent for all 8 byte versions. ordering information part number organization speed leads dimension power IBM11T2645HP-60t 2mx64 60ns au 2.66x1.0x 0.149 3.3v IBM11T2645HP-6rt 2mx64 60ns au 2.66x1.0x 0.149 3.3v IBM11T2645HP-70t 2mx64 70ns au 2.66x1.0x 0.149 3.3v discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 32 block diagram v cc v ss d0 - d7 d0 - d7 we ras0 oe dq16 dq17 dq18 dq19 ras we oe d1 cas1 dq20 dq21 dq22 dq23 dq0 dq1 dq2 dq3 ras we oe d0 cas0 dq4 dq5 dq6 dq7 a0 - a10 a0 - a10: dram d0 - d7 dq24 dq25 dq26 dq27 ras we oe d3 cas3 dq28 dq29 dq30 dq31 dq8 dq9 dq10 dq11 ras we oe d2 cas2 dq12 dq13 dq14 dq15 dq40 dq41 dq42 dq43 ras we oe d5 cas5 dq44 dq45 dq46 dq47 dq32 dq33 dq34 dq35 ras we oe d4 cas4 dq36 dq37 dq38 dq39 dq56 dq57 dq58 dq59 ras we oe d7 cas7 dq60 dq61 dq62 dq63 dq48 dq49 dq50 dq51 ras we oe d6 cas6 dq52 dq53 dq54 dq55 a1 a2 a0 sda scl serial eeprom discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 32 50h7630 sa14-4460-04 revised 4/97 truth table function ras cas we oe row address column address dqx standby h x x x x x high impedance read l l h l row col valid data out early-write l l l x row col valid data in late-write l l h ? l h row col valid data in rmw l l h ? ll ? h row col valid data in/out edo page mode - read 1st cycle l h ? l h l row col valid data out subsequent cycles l h ? l h l n/a col valid data out edo page mode - write 1st cycle l h ? l l x row col valid data in subsequent cycles l h ? l l x n/a col valid data in edo page mode - rmw 1st cycle l h ? lh ? ll ? h row col valid data in/out subsequent cycles l h ? lh ? ll ? h n/a col valid data in/out ras-only refresh l h x x row n/a high impedance cas-before- ras refresh h ? l l h x x x high impedance hidden refresh read l ? h ? l l h l row col data out write l ? h ? l l h x row col data in self refresh h ? l l h x x x high impedance discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 32 serial presence detect spd entry value serial pd data entry (hexadecimal) byte # description 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type edo 02 3 number of row addresses on assembly 11 0b 4 number of column addresses on assembly 10 0a 5 number of dimm banks 1 01 6 - 7 data width of assembly x64 4000 8 voltage interface level of this assembly lvttl 01 9 ras access 60ns 3c 70ns 46 10 cas access 15ns 0f 17ns 11 20ns 14 11 dimm configuration type non-parity 00 12 refresh rate/type sr/4x (62.5 us) 84 13 primary dram data width x8 08 14 error checking dram data width n/a 00 15 - 62 reserved undefined 00 63 checksum for bytes 0 - 62 checksum data cc 64 - 71 manufacturers jedec id code ibm a400000000000000 72 module manufacturing location toronto, canada 91 vimercate, italy 53 73 - 90 module part number ascii 11t2645hpr-60t 313154323634354850rr2d36305420202020 ascii 11t2645hpr-6rt 313154323634354850rr2d36525420202020 ascii 11t2645hpr-70t 313154323634354850rr2d37305420202020 91 - 92 module revision code r plus ascii blank rr20 93 - 94 module manufacturing date week/year code wwyy 95 - 98 module serial number serial number ssssssss 99 - 127 reserved undefined 00 128 - 255 open for customer use undefined 00 cc = checksum data byte, 00-ff (hex) r = alphanumeric revision code, a-z, 0-9 rr = ascii coded revision code byte r ww = binary coded decimal week code, 01-52(decimal) ? 01-34 (hex) yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex) ss = serial number data byte, 00-ff (hex) discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 32 50h7630 sa14-4460-04 revised 4/97 absolute maximum ratings symbol parameter rating units notes v cc power supply voltage -0.5 to +4.6 v 1 v in input voltage -0.5 to min (v cc + 0.5, 4.6) v1 v in/out(spd) input voltage(serial pd device) -0.3 to 6.5 v 1 v out output voltage -0.5 to min (v cc + 0.5, 4.6) v1 t opr operating temperature 0 to +70 c 1 t stg storage temperature -55 to +150 c 1 p d power dissipation 3.6 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated is not implied. exposure to absolute maximum rating con- dition for extended periods may affect reliability. recommended dc operating conditions (t a = 0 to 70 c) symbol parameter min typ max units notes v cc supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v cc + 0.5 v 1, 2 v ih(spd) input high voltage(serial pd device) v cc x 0.7 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 v 1, 2 v il(spd) input low voltage(serial pd device) -0.3 v cc x 0.3 v 1, 2 v ol(spd) output low voltage(serial pd device) i ol = 3ma 0.4 v 1. all voltages referenced to v ss. 2. v ih may overshoot to v cc + 1.2v for pulse widths of 4.0ns . additionally, v il may undershoot to -1.2v for pulse widths 4.0ns. pulse widths measured at 50% points with amplitude measured peak to dc reference. capacitance (t a = 0 to +70 c, v cc = 3.3v 0.3v) symbol parameter max units c i1 input capacitance ( a0-a9) 55 pf c i2 input capacitance ( ras, we, oe) 68 pf c i3 input capacitance ( cas) 12 pf c i4 input capacitance ( scl) 8pf c io1 input/output capacitance (dq0-63) 11 pf c io2 input/output capacitance (sda) 10 pf discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 32 dc electrical characteristics (t a = 0 to +70?c, v cc = 3.3v 0.3v) symbol parameter min. max. units notes i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min.) -60/-6r 720 ma 1, 2, 3 -70 640 i cc2 standby current (ttl) power supply standby current ( ras = cas = v ih ) 16.1 ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas = v ih : t rc = t rc min) -60/-6r 720 ma 1, 3 -70 640 i cc4 edo page mode current average power supply current, edo page mode ( ras = v il , cas, address cycling: t pc = t pc min) -60/-6r 400 ma 1, 2, 3 -70 320 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) 1.7 ma i cc6 cas before ras refresh current average power supply current during self refresh cbr cycle with ras, cas, cycling: t rc = t rc min) -60/-6r 720 ma 1, 3 -70 640 i cc7 self refresh current average power supply current during self refresh cbr cycle with ras 3 t rass (min); cas held low; we = v cc -0.2v; addresses and d in = v cc -0.2v or 0.2. 1.6 ma i i(l) input leakage current input leakage current, any input (0.0 v in (v cc + 0.3v)), all other pins not under test = 0v x=y ras, we, oe, add -80 +80 m a cas -10 +10 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -10 +10 m a v oh output level (ttl) output h level voltage ( i out = -5ma) 2.4 v cc v v ol output level (ttl) output l level voltage ( i out = +4.2ma) 0.0 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 and i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras =v il . in the case of i cc4 , it can be changed once or less when cas =v ih . discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 32 50h7630 sa14-4460-04 revised 4/97 ac characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v) 1. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. 2. ac measurements assume t t =2ns. 3. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 4. valid column addresses are a0 through a9. 5. ac measurements assume t t =2ns. read, write, read-modify-write and refresh cycles (common parameters) symbol parameter -60 -6r -70 unit notes min max min max min max t rc random read or write cycle time 104 104 124 ns t rp ras precharge time 40 40 50 ns t cp cas precharge time 10 10 10 ns t ras ras pulse width 60 10k 60 10k 70 10k ns t cas cas pulse width 10 10k 10 10k 12 10k ns t asr row address setup time 0 0 0 ns t rah row address hold time 10 10 10 ns t asc column address setup time 0 0 0 ns t cah column address hold time 10 10 12 ns t rcd ras to cas delay time 14 45 14 43 14 50 ns 1 t rad ras to column address delay time 12 30 12 30 12 35 ns 2 t rsh ras hold time 10 10 12 ns t csh cas hold time 50 50 55 ns t crp cas to ras precharge time 5 5 5 ns t oed oe to d in delay time 151520 ns 3 t dzo oe delay time from d in 0 0 0 ns 4 t dzc cas delay time from d in 0 0 0 ns 4 t t transition time (rise and fall) 2 30 2 30 2 30 ns 1. operation within the t rcd (max) limit ensures that t rac (max) can be met. the t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled by t cac. 2. operation within the t rad (max) limit ensures that t rac (max) can be met. the t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa. 3. either t cdd or t oed must be satis?ed. 4. either t dzc or t dzo must be satis?ed. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 32 write cycle symbol parameter -60/-6r -70 unit notes min max min max t wcs write command set up time 0 0 ns 1 t wch write command hold time 10 12 ns t wp write command pulse width 10 12 ns t rwl write command to ras lead time 10 12 ns t cwl write command to cas lead time 10 12 ns t ds d in setup time 00ns 2 t dh d in hold time 10 12 ns 2 1. t wcs , t rwd , t cwd , t awd , and t cpw are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpw 3 t cpw (min.)(fast page mode), the cycle is a read- modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the con- dition of the data (at access time) is indeterminate. 2. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-modify-write cycles. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 32 50h7630 sa14-4460-04 revised 4/97 read cycle symbol parameter -60 -6r -70 unit notes min max min max min max t rac access time from ras 60 60 70 ns 1, 2, 3 t cac access time from cas 15 17 20 ns 1, 3 t aa access time from address 30 30 35 ns 1 t oea access time from oe 15 17 20 ns 3 t rcs read command setup time 0 0 0 ns t rch read command hold time to cas 000ns 4 t rrh read command hold time to ras 000ns 4 t ral column address to ras lead time 30 30 35 ns t clz cas to output in low-z 0 0 0 ns 3 t oes oe setup time prior to cas 555ns t ord oe setup time prior to ras (hidden refresh) 0 0 0 ns t cdd cas to d in delay time 15 15 20 ns 7 t oez output buffer turn-off delay from oe 15 15 20 ns 5 t off output buffer turn-off delay 15 15 20 ns 5, 6 1. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 2. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?ed as a reference point only. if t rad is greater than the speci?ed t rad (max.) limit, then access time is controlled by t aa . 3. measured with the speci?ed current load and 100pf at v ol = 0.8v and v oh = 2.0v. 4. either t rch or t rrh must be satis?ed for a read cycle. 5. t off (max) and t oez (max) de?ne the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. either t cdd or t oed must be satis?ed. 7. t off is referenced from the rising edge of ras or cas , whichever is last. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 32 read-modify-write cycle symbol parameter -60 -6r -70 unit notes min max min max t rwc read-modify-write cycle time 135 135 162 ns t rwd ras to we delay time 79 79 94 ns 1 t cwd cas to we delay time 34 36 44 ns 1 t awd column address to we delay time 49 49 59 ns 1 t oeh oe command hold time 10 10 12 ns 1. t wcs , t rwd , t cwd , t awd , and t cpw are not restrictive parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.), t awd 3 t awd (min.) and t cpw 3 t cpw (min.)(fast page mode), the cycle is a read- modify-write cycle and the data will contain read from the selected cell: if neither of the above sets of conditions are met, the con- dition of the data (at access time) is indeterminate. edo mode cycle symbol parameter -60/-6r -70 units notes min. max. min. max. t hcas cas pulse width (edo page mode) 10 10k 12 10k ns t hpc edo page mode cycle time (read/write) 25 30 ns t hprwc edo page mode read modify write cycle time 60 72 ns t doh data-out hold time from cas 5 5 ns t whz output buffer turn-off delay from we 0 10 0 15 ns t wpz we pulse width to output disable at cas high 10 10 ns t cprh ras hold time from cas precharge 35 40 ns t cpa access time from cas precharge 35 40 ns 1 t rasp edo page mode ras pulse width 60 125k 70 125k ns t oep oe high pulse width 10 10 ns t oehc oe high hold time from cas high 10 10 ns 1. measured with the specified current load and 100pf at v ol = 0.8v and v oh = 2.0v. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 32 50h7630 sa14-4460-04 revised 4/97 refresh cycle symbol parameter -60/-6r -70 unit notes min max min max t chr cas hold time ( cas before ras refresh cycle) 55ns t csr cas setup time ( cas before ras refresh cycle) 1010ns t wrp we setup time ( cas before ras refresh cycle) 1010ns t wrh we hold time ( cas before ras refresh cycle) 1010ns t rpc ras precharge to cas hold time 5 5 ns t ref refresh period 128 128 ms 1 1. 2048 refreshes are required every 128ms. self refresh cycle symbol parameter -60 -70 unit notes min max min max t rass ras pulse width during self refresh cycle 100 100 m s 1 t rps ras precharge time during self refresh cycle) 104 124 ns 1 t chs cas hold time during self refresh cycle) 50 50 ns 1, 2 t chd cas hold time from ras falling during self refresh cycle 350 350 m s 1, 2 1. when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed in an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed imme- diately before entry to and immediately after exit from self refresh. 2. if t rass >t chd (min) then t chd applies. if t rass t chd (min) then t chs applies. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 32 presence detect read and write cycle symbol parameter -70 unit notes min max f scl scl clock frequency 80 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 7.0 m s t buf time the bus must be free before a new transmission can start 6.7 m s t hd:sta start condition hold time 4.5 m s t low clock low period 6.7 m s t high clock high period 4.5 m s t su:sta start condition setup time(for a repeated start condition) 6.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 500 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 6.7 m s t dh data out hold time 300 ns t wr write cycle time 15 ms 1 1. the write cycle time(twr) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 32 50h7630 sa14-4460-04 revised 4/97 read cycle ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rcs t dzc t clz t cac t rac hi-z hi-z t rrh : h: or l t rcd t oez hi-z t rsh t ral t dzo t aa t oea cas t oed t cdd t rch t off t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 32 write cycle (early write) t rc ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rcd t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wch t ds t dh t cas t rsh t wp cas t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 32 50h7630 sa14-4460-04 revised 4/97 write cycle (late write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rwl : h or l t wp t cwl valid data in hi-z hi-z t dzo t oez t clz t ds t rcd t dh t rcs * * t oeh greater than or equal to t cwl hi-z t rsh t dzc t oea t oeh t oed cas t wrp note 1 t wrp t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 32 read-modify-write-cycle d in t oeh v ol v oh v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih t rcd t rwc t ras t csh t cas t rp t rah t asc t asr t cah t cwd t rcs t oea t rwl t cwl t wp t dh t ds t dzc t cac t clz t oed t oez t rac ras address we oe d in d out hi-z hi-z d out row column : h or l * t oeh greater than or equal to t cwl * hi-z t crp t awd t aa t rwd t rsh t rad t dzo cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 32 50h7630 sa14-4460-04 revised 4/97 edo page mode read cycle t rp t hcas data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t doh t doh t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t wp t cac data out n t off cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 32 edo page mode read cycle ( oe control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off t oea t oez t oez t oea cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes t hcas t oes t oehc t oep t oehc t oep t oes discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 32 50h7630 sa14-4460-04 revised 4/97 edo page mode read cycle ( we control) t rp data out 1 data out 2 oe we ras row address column 1 column 2 column n t oea t oez t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t oes t hcas t wpz t wpz t rch t rcs t rcs t rch t whz t whz discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 32 edo page mode early write cycle t hcas t rp ras row address we column 1 column 2 column n data in 1 data in 2 data in n t asr t rah t cah t wch t dh d in t rasp t rsh t hcas t hcas t hpc t rad t asc t asc t csh t cah t asc t cah t wch t wcs t wch t wcs t wcs t ds t ds t dh t dh t ds : h or l t cwl t rwl t wp t wp t wp oe = dont care v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t ral discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 32 50h7630 sa14-4460-04 revised 4/97 edo page mode late write cycle t hcas t rp ras row address we column 1 column 2 column n oe data in 1 data in 2 data in n t asr t rah t asc t asc t asc t cah t cah t cah t cwl t wp t cwl t wp t cwl t wp t oeh t oeh t oeh t ds t dh t oed t ds t dh t oed t ds t dh d in : h or l t rasp t rsh t hcas t hcas t hpc t csh t oed hi-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp t rad t rcs t rcs t rcs t rwl cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 32 edo page mode read modify write cycle address ras we oe d out d in d in d in t rp t cp t cp t asr t rad t rah t cah t asc t asc t cah t asc t cah t wp t cwl t wp t rcs t rcs t wp t cwl t rwl t cac t oeh t oeh t oeh d out d out t clz t clz t oed t oed t dh t dh t clz t oed t dh d in d out : h or l hi-z hi-z t rasp t cas t hprwc t cas t ral t awd t cwd t aa t cpa t aa t awd t cwd t rwd t awd t cwd t rcs t rac t aa t oea t oea t cac t cac t oea t oez t oez t ds t ds t ds column 1 row column 2 column n t csh t oez v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t cas t crp t cpa cas t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 32 50h7630 sa14-4460-04 revised 4/97 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z : h or l note: we, oe, d in are h or l t rpc t crp cas discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 32 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp oe v ih v il d out v oh v ol hi-z : h or l t off t oez hi-z t oed t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd cas t rpc t csr t wrh t wrp t csr discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 32 50h7630 sa14-4460-04 revised 4/97 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t oed t oez t cdd t clz t cac t rac hi-z hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t dzo t ral t off cas t oea t ord t aa discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 32 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il oe v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd cas discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 28 of 32 50h7630 sa14-4460-04 revised 4/97 self refresh cycle (sleep mode) ras v ih v il v ih v il we v ih v il t rass t rps t crp d out v oh v ol hi-z : h or l t off t cp t csr t wrh t wrp t rpc t chd t chs notes: 1. address and oe are h or l 2. once ras (min) is provided and ras remains low, the dram will be in self refresh, commonly known as sleep mode. 3. if t rass > t chd (min) then t chd applies. u cas l cas discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 29 of 32 presence detect operation clock and data conventions : data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figure 1 & fig- ure 2). start condition : all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the serial pd device contin- uously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition : all communications are terminated by a stop condition, which is a low to high transi- tion of sda when scl is high. the stop condition is also used to place the serial pd device into standby power mode. acknowledge : acknowledge is a software conven- tion used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the pd device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write opera- tion have been selected, the pd device, will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the pd device will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data trans- missions and await the stop condition to return to standby power mode. presence detect (eeprom) bus timing scl sda in t su:sto t hd:sta t su:sta t aa sda out t f t low t high t r t su:dat t hd:dat t buf t dh figure 1. data window figure 2. de?nition of start & stop figure 3. acknowledge response from receiver scl sda data data stable data stable change scl sda start stop bit bit acknowledge scl from data output from trans data output from receiver 89 master m discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 30 of 32 50h7630 sa14-4460-04 revised 4/97 layout drawing 67.60 2.661 (2x) 0 1.800 .0709 3.30 .1299 63.60 2.504 32.80 1.293 2.00 min .0787 front 4.00 .157 25.4 20.00 1.00 .7874 3.80 max 0.1496 side 6.215 1.00 + _ .039 + _ 0.10 .0039 .2447 min 6.00 .236 23.2 .9134 24.5 .9646 4.60 .1811 2.50 .0984 4.00+/- 0.10 .1575+/-.0039 1.50+/- 0.10 .0591+/-.0039 0.60+/- .05 width .0236 0.80 typ pitch .0315 2.55 .1004 0.25 max 0.009 2m x 8 thin luna tsop note: all dimensions are typical unless otherwise stated. millimeters inches discontinued (9/98 - last order; 3/99 last ship)
IBM11T2645HP 2m x 64 144 pin so dimm 50h7630 sa14-4460-04 revised 4/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 31 of 32 revision log rev contents of modi?cation 1/96 initial release. 4/96 correct typos 8/96 changed dram retention time 11/96 corrected cbr timing diagram changed t odd to t oed 4/97 update serial presence detect table discontinued (9/98 - last order; 3/99 last ship)
intern ational business machines corp.1997 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. sa14-4460-04 a discontinued (9/98 - last order; 3/99 last ship)

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